Principal Physical Design

About This Role

Planning and running the physical design of advanced DRAM digital designs is the core of this principal engineering role, with a strong focus on timing closure, power integrity, EMIR analysis, and design reliability. The engineer will develop scalable physical design solutions that achieve power, performance, area (PPA), and reliability targets for next-generation memory products, and will lead methodology innovation, mentor engineers, and influence the future roadmap for physical design and power integrity across the organization.

Responsibilities

• Lead physical design implementation of complex DRAM digital designs, including floorplanning, place and route, clock tree synthesis, timing closure, and tapeout activities
• Drive power integrity strategies and signoff methodologies, including PDN planning, IR drop analysis, electromigration (EM) verification, and EMIR signoff
• Collaborate with multi-functional teams to resolve timing, congestion, power, signal integrity, and reliability challenges at both block and full-chip levels
• Develop and deploy methodology improvements, automation solutions, and guidelines to improve build quality, efficiency, and scalability
• Mentor engineers and provide technical leadership while influencing future memory products through innovation in physical design and signoff methodologies

Requirements

• Master's degree in Electrical Engineering (or equivalent) with 8+ years of experience, or Bachelor's degree with 10+ years of experience in ASIC physical design
• Strong expertise in physical design implementation flows including floorplanning, place and route, clock tree synthesis, timing closure, and design signoff
• Hands-on experience with STA, signal integrity, power integrity, physical verification, and advanced process technologies
• Proficiency with industry-standard physical design and signoff tools such as Synopsys IC Compiler II (ICC2), Fusion Compiler, PrimeTime, PrimePower, and RedHawk (or equivalent)
• Strong scripting and automation skills using Python, Tcl, or similar languages
• Demonstrated ability to drive multi-functional technical initiatives and influence engineering organizations

Nice to have:

• Experience developing physical design, power delivery network (PDN), or EMIR methodologies for large-scale ASIC, SoC, or memory products
• Expertise in power integrity signoff, including static and dynamic IR drop analysis, electromigration verification, current profiling, and IDD modeling
• Experience driving methodology transformation, tool deployment, and engineering process improvements across organizations
• Demonstrated technical leadership, mentoring, and ownership of projects across multiple product generations
• Strong communication, problem-solving, and collaboration skills, with experience bringing to bear AI-assisted technologies and Generative AI tools to improve engineering efficiency and innovation