About the role
Job Description 按照模拟电路设计图，完成版图的设计及相应的LVS/DRC等物理验证检查 1. 具备模拟IC版图经验； 2. 具备IP整合经验的优先； 3. 熟悉Virtuoso ，laker ，calibre等工具的优先； 4. 具备ESD和latch up 效应防护经验的优先； 5. 掌握先进制程版图经验的优先。
Main Requirements and Qualifications
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- 本科，电子信息工程类、Electronic Information、Engineering等相关专业优先；
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- 1年以内经验，可接收26届应届生。
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