About the role
Expert level verification engineer with strong SystemVerilog and UVM experience. As an alternative to SystemVerilog/UVM, we are open to candidates with a verification background in lab testing and/or design verification testing. Experience with design on Xilinx products would be a strong plus.
Required Skills:
• Expert level verification engineer with strong SystemVerilog and/ or UVM experience or
• FPGA verification in lab testing and/or Hardware FPGA design verification testing
• Experience with design on Xilinx products would be a strong plus
• expected to communicate effectively with emerging engineers at the offshore team, GETC I site and provide both technical and process guidance to the verification team.
Core Responsibilities
• RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
• Verification: Create UVM constrained random environments and conduct static timing, linting, and clock-domain-crossing (CDC) analyses.
• Hardware Lifecycle: Handle requirements capture, decomposition, architecture development, synthesis, and placement & routing.
Key Qualifications
• Experience: Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior designation).
• Education: Degree in a STEM (Science, Technology, Engineering, Mathematics) field.
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