Engineer, Design Verification

About This Role

This design verification engineering role involves end-to-end verification execution for System-on-Chip (SoC) designs, focusing on complex digital IPs and subsystems from specification to sign-off. The position suits an engineer with expertise in UVM-based verification environments and a strong understanding of SystemVerilog and assertions.

Responsibilities

• Be a part of end-to-end verification execution for SoC, owning complex digital IPs and subsystems from specification to sign-off
• Define and drive IP-level verification strategies, including test plans, coverage models, and closure criteria
• Develop scalable, reusable UVM-based verification environments for IP and subsystem verification
• Lead functional, code, assertion, and cross-coverage closure, ensuring high-quality sign-off with clear metrics
• Apply AI/ML-assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency
• Drive constraint random and directed test methodologies for thorough protocol, corner-case, and stress verification
• Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration
• Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
• Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors
• Work with EDA vendors to evaluate and adopt next-generation verification, coverage, and analytics tools
• Support Gate-Level Simulation (GLS), low-power verification, and post-silicon debug when required
• Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration

Requirements

• Bachelor’s or master’s degree in Electronics Engineering
• 1 - 2 years of experience in SoC Verification domains and working knowledge of industry standard EDA toolkits
• Strong expertise in UVM-based testbench architecture and development
• Proven experience in metric-driven verification, including functional and code coverage closure
• Deep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices
• Experience with directed and constrained-random verification methodologies
• Experience debugging complex design issues in simulation, emulation, and post-silicon environments
• Proficiency in Verilog/SystemVerilog, with working knowledge of C/C++, Shell scripting
• Strong analytical, problem-solving, and communication skills

Nice to have:

• Hands-on experience using AI/ML-based verification tools for coverage gap analysis, test stimulus optimization, and regression triage and coverage acceleration