DFT Design Engineer

About This Role

Designing and verifying DFT features for silicon chips is the core of this engineering role, which involves working with scan architecture, ATPG, JTAG, and Memory BIST. This position suits an engineer with experience in gate-level simulations and debugging DFT issues, who can also collaborate with post-silicon teams.

Responsibilities

• Implement and verify DFT features including JTAG, Memory BIST/Repair
• Perform gate-level simulations with timing annotations
• Debug DFT issues, simulation failures, and DRC
• Improve ATPG coverage
• Collaborate with post-silicon/manufacturing teams on ATE debugging and issue resolution

Requirements

• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering
• 2+ years of DFT experience
• Strong knowledge and experience in Spyglass DFT, Scan Architecture (SSN Topology), ATPG, and various fault models
• Hands-on skills to implement JTAG, Memory BIST, and Memory Repair (BIRA/BISR) circuitry using industry-standard tools
• Hands-on experience in DFT verification using Gate Level Simulations with timing annotations
• Good understanding of timing constraints and DFT mode timing analysis
• Proficiency in RTL coding and shell scripting

Important Details

• Shift: Shift 1 (India)
• Work model: hybrid, allowing employees to split time between on-site at an assigned Intel site and off-site

About the Company

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.